The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventor(s), to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A memory system (e.g., a flash memory system) generally includes a decoder to decode data read from a memory. The decoder, for example, uses iterative soft decoding algorithms. For example, the decoder employs error correcting codes (ECC) such as low density parity check (LDPC) codes, Reed-Solomon (RS) codes, Turbo codes, or the like.
Errors in a memory system can include hard errors and soft errors. A log-likelihood ratio (LLR) for a memory cell is associated with a probability of a data bit in the memory cell being equal to 1 or 0. An error in estimation of a LLR for a memory cell, as a result of a hard error in the memory cell, is usually significant, for example, compared to an error in estimation of an LLR as a result of a soft error. Due to the significant error in the estimation of the LLR associated with a hard error, performance of a soft decoding algorithm (e.g., LDPC codes) deteriorates significantly in presence of hard errors in the data to be decoded, even if only a limited number of hard errors are present in the data. Performance of the soft decoding algorithm deteriorates significantly even if the hard error rate in the data is relatively low.